1. Field of the Invention
The present invention relates to a pulse generating circuit, and more particularly to a pulse signal generating circuit built in a microcomputer system and generating a pulse signal as an output signal from the system.
2. Description of the Prior Art
The pulse signal alternately generating a high level signal and a low level signal is used as various control signals for, for example, an actuator by, for example, PWM (Pulse Width Modulation).
FIG. 1 is a block diagram exemplary of a conventional pulse generating circuit housed in a one-chip microcomputer for mainly carrying out the real time processing, which is disclosed in the U.S. Pat. No. 4,326,247.
In FIG. 1, a reference numeral 1 designates a CPU (Central Processing Unit) at the microcomputer, which outputs various data signals to a data bus 3 and introduces data therefrom.
A reference numeral 2 designates a counter, which is connected with the CPU 1 through the data bus 3. The counter 2 is given at a clock terminal CK thereof clock as a counting object, generated at a clock generating circuit 4 to be discussed later, and also starts counting from zero, for example, so that the counted value, when it reaches a predetermined value, overflows to be reset zero and sends a predetermined signal to the CPU 1.
A reference numeral 4 designates a clock generating circuit, which generates clock pulse, being a basic action of the micro computer, and gives it to the CPU 1 and counter 2 through a clock line 5.
A reference numeral 6 designates a comparison value register, which is connected to the CPU 1 through the data bus 3. The comparison value for defining the time for converting a level of output pulse is set at the comparison value register 6 by the CPU 1.
A reference numeral 7 designates a digital comparator. The digital comparator 7 is given at a first input a counting value of the counter 2 and at a second input the comparison value set in the aforesaid comparison value register 6, and compares both the digital inputs, and outputs a coincidence signal CO to a port buffer 8 when both the inputs are coincident with each other.
At the port buffer 8 is set by the CPU 1 the data signal, that is, a logical "1" or "0", corresponding to the high level or the low level signal of the pulse output to be lastly outputted, and the port buffer 8, when given the coincidence signal CO from the aforesaid digital comparator 7, gives the set data signal to an output latch circuit 9.
The output latch circuit 9 latches the data signal given from the port buffer 8 and feeds it to an output terminal OT, which outputs an output level of pulse signal, that is, the high or low level signal, corresponding to the data signal.
Explanation will be given on operation of the conventional pulse generating circuit with reference to the timing chart in FIG. 2.
The counter 2 always counts the clock signals given from the clock generating circuit 4 and increments the counting value one by one per one clock, the counting value of counter 2, as shown in the upper half of FIG. 2, repeats the operation such that the value increases from zero to the predetemined value so as to overflow and the counting value is reset to zero.
For example, when the output pulse from the output terminal OT is at a low level as shown in the left end of FIG. 2, in order to define the time (T23 in FIG. 2) when the output pulse from the output terminal OT is to be converted to a high level, the comparison value is set at the comparison value register 6 through the data bus 3 from the CPU 1(the timing of T21 in FIG. 2). In addition, the comparison value of course is included between the counting value of zero and the overflow value of the counter 2.
Furthermore, in the port buffer 8 is written the data, concretely a logical "1", for defining the level of pulse to be outputted after the level conversion time T23 of the output pulse defined by the aforesaid comparison value (the timing T22 in FIG. 2).
Thus, initialization of the time and level for converting the level of the output pulse is finished. In addition, the initialization is initiated by a signal given to the CPU 1 due to an overflow of the counter 2.
After the aforesaid initialization, when the counting value of counter 2 reaches the comparison value set at the comparison value register 6 (the timing T23 in FIG. 2), the digital comparator 7 detects coincidence of both the values so as to give a coincidence signal CO to the port buffer 8. Hence, the data "1" written in the port buffer 8 is latched by the output latch circuit 9 and a high level signal corresponding to the data is outputted from an output terminal OT, in other words, the output pulse from the output terminal OT is converted from the low level to the high level.
The conventional pulse generating circuit, which is constructed as above-mentioned, has several problems as follows:
Generally, the pulse signal requires variation in its cycle period and pulse width (duty), in both of which the conventional pulse generating circuit is problematical.
The first problem is that it is required for converting the level of pulse output to inevitably write the comparison value in the comparison value register 6 and the data in the port buffer 8 prior to the time to carry out the level conversion, as shown in FIG. 2. Since these processings both are excecuted in a software manner by the CPU 1, the time required for the execution depends on the program processing speed of CPU 1. Accordingly, when the pulse signal, after converted from one level to the other, is converted again to the one level, a time over a certain extent is required. In other words, a width of pulse outputted from the output terminal OT cannot be smaller than the sum of the time needed for writing the comparison value in the comparison value register 6 by the CPU 1 and the time needed for writing the data in port buffer 8. More concretely, for example in FIG. 3, when the comparison value V31 is written in the comparison value register 6 at the timing T31 and the data "1" in the port buffer 8 at the timing T32, the level of pulse is converted from the low to high at the timing T33. Thereafter, even when the level of pulse output is immediately again converted to the low level, the write-in of comparison value V32 in the comparison value register 6 is completed at the timing T34, and that of data "0" in the port buffer 8, at the timing T35. Hence, it is impossible before the timing T35 to convert the pulse output to the low level. In other words, the time duration, that is, the pulse width, in which the level conversion, after the level is converted from one level to the other, is carried out again to the one level, cannot be shorter than a time duration from the timing T33 to T35 shown in FIG. 3.
The second problem is that the counting start value and overflow value of the counter 2 are fixed. Therefore, in a case where the level conversion of the output pulse is carried out at a cycle period different from the one from the counting start of counter 2 until the counter 2 overflows to be reset, it is required to compute at each one cycle period of pulse output the comparison value to be set in the comparison value register 6. Accordingly, when the cycle duration of pulse output is relatively shorter, the overhead time with respect to CPU 1 increases to cause reduction of a throughput of the entire apparatus.